In the past thirty years, an integrated circuit (IC) has increased 100,000 times the memory capacity and 2,000 times the logic operational speed. This happened, due to the increasingly reduced dimension of its main component metal oxide semiconductor field effect transistor (MOSFET), the increase in memory capacity and a logic operational speed far beyond expectation.
However, when the dimension of the CMOS device reduces to reach a technology node below 45 nm˜65 nm, a gate dielectric layer must be thin, about 1.2 nm˜1.5 nm, in order to keep a considerable gate capacitance and reduce the power consumption of a single device with a substantially small leakage current. A conventional gate dielectric layer is made of SiO2. When the SiO2 dielectric layer has the above thickness, direct tunneling will occur to lead to a duly high leakage current, which is in contrast to the feature's trend.
As a high-k gate dielectric material, HfO2 or ZrO2 is potentially advantageously used. However, the crystallization temperature is not high, about 700° C., which is adversely affected by high temperature during the formation of the device and thus the properties of the device are deteriorated, due to crystallization. Adding elements such as Al, N or Si into the dielectric material has made an improvement. A typical Physical Vapor Deposition (PVD) usually sputters over a constant-composition substrate or a plurality of different substrates. Oxygen plasma used in the deposition process tends to react with the silicon substrate to form an interfacial oxide. In a Chemical Vapor Deposition (CVD) process, doping those elements is difficult, and therefore there is a need to find a complex precursor. Impurities such as Cl, generated at the same time the complex precursor has been formed, are removed by using high-temperature annealing, which may increase the thickness of the dielectric layer. In order to overcome the above problems, dry oxidation over Hf metal or low-temperature plasma oxidation is used.
The formation of the dielectric layer in the transistor has been well disclosed in, for example, U.S. Pat. No. 6,559,051. In '051, electroless plating that uses a precursor-containing solution to form a metal thin layer is performed, and then oxidation is performed. However, such a method allows oxygen ions in the solution to contact the silicon substrate at the beginning to form oxides that increase the thickness of the dielectric layer.